San Jose, CA—Kioxia Corporation and Western Digital Corp. developed their sixth-generation, 162-layer 3D flash memory technology. Marking the next milestone in the companies’ 20-year joint venture, this is the highest density and most advanced 3D flash memory technology to date. Consequently, it answers the ever-increasing need for faster transfer rates. 
The companies detailed the innovations in a joint presentation at the ISSCC 2021 conference. “Through our strong partnership that has spanned two decades, Kioxia and Western Digital have successfully created unrivaled capabilities in manufacturing and R&D,” commented Masaki Momodomi, chief technology officer at Kioxia.
“Together, we produce over 30% of the world’s flash memory bits; we are steadfast in our mission to provide exceptional capacity, performance and reliability at a compelling cost. We each deliver this value proposition across a range of data-centric applications from personal electronics to data centers as well as emerging applications enabled by 5G networks, artificial intelligence and autonomous systems.”
3D Flash Memory Innovation
This sixth-generation 3D flash memory features advanced architecture beyond conventional eight-stagger memory hole array. In addition, it achieves up to 10% greater lateral cell array density compared to the fifth-generation technology. Consequently, this lateral scaling advancement, in combination with 162 layers of stacked vertical memory, enables a 40% reduction in die size compared to the 112-layer stacking technology, optimizing cost.
“As Moore’s Law reaches its physical limits across the semiconductor industry, there’s one place where Moore’s Law continues its relevancy; that’s in flash,” said Dr. Siva Sivaram, president of Technology & Strategy, Western Digital. “To continue these advances and meet the world’s growing data demands, a new approach to 3D flash memory scaling is critical.
“With this new generation, Kioxia and Western Digital are introducing innovations in vertical as well as lateral scaling to achieve greater capacity in a smaller die with fewer layers. This innovation ultimately delivers the performance, reliability as well as cost that customers need.” 
The Kioxia and Western Digital teams also applied Circuit Under Array CMOS placement and four-plane operation. Together deliver nearly 2.4 times improvement in program performance. They also achieve a 10% improvement in read latency compared to the previous generation. I/O performance was also improved by 66%; thus, it enables the next-generation interface to support the ever-increasing need for faster transfer rates.
Overall, the new 3D flash memory technology reduces the cost per bit. It also increases the manufactured bits per wafer by 70% compared with the previous generation.
